1. Field of the Invention
Exemplary embodiments of the present invention relate to a semiconductor package and a method for selecting a chip in a semiconductor package, and more particularly, to a stack package including through-silicon vias, which uses a cantilever to allow a semiconductor chip to be easily selected, and a method for selecting a chip of a stack package.
2. Description of the Related Art
Recently, as electronic products trend toward miniaturization and high performance and demand for portable mobile products increases, demand for an ultra-miniaturized semiconductor memory with large capacity has increased. In general, attempts to increase storage capacity of a semiconductor memory may be divided into a method of increasing a degree of integration of a semiconductor chip and a method of mounting a plurality of semiconductor chips in one semiconductor package. In the former case, significant effort, cost and time are required to increase the degree of integration. However, in the latter case, if it is possible to mount a plurality of semiconductor chips in one package, this may increase storage capacity of a semiconductor memory by changing only a packaging method. Also, in the latter case, a number of advantages are provided in terms of investment cost, research and development, and required time when compared to the former case. Semiconductor memory manufacturers have made efforts to increase the storage capacity of a semiconductor memory device by using a multi-chip package which is manufactured in such a manner that a plurality of semiconductor chips are mounted in one semiconductor package.
Methods for mounting a plurality of semiconductor chips in one semiconductor package are divided into horizontally mounting semiconductor chips and vertically mounting semiconductor chips. Due to the characteristics of electronic products which trend toward miniaturization, most semiconductor memory manufacturers prefer a stack type multi-chip package in which semiconductor chips are packaged in such a way as to be vertically stacked.
While a stack type multi-chip package technology provides advantages in that the manufacturing cost of a package can be reduced through a simplified process and mass production is possible, disadvantages are caused in that spaces for forming electrical connections in the package becomes insufficient due to an increase in the number and the size of chips to be stacked. Typically, a conventionally stacked multi-chip package is manufactured such that a plurality of chips are disposed in a chip region of a substrate and the bonding pads of the respective chips and the conductive circuit patterns of the substrate are electrically connected using wires. Consequently, spaces are required for wire bonding and areas are needed for the wires to connect to circuit patterns of the substrate, which may result in an increase in the size of a semiconductor package. In consideration of these facts, a package structure using through-silicon vias (TSVs) has been suggested as an example of the stack type multi-chip package. A package using through-silicon vias has a structure in which through-silicon vias are formed in the chips at a wafer level and physical and electrical connections are formed vertically between the chips using the through-silicon vias. Researches for a package adopting through-silicon vias have been conducted so as to accommodate the trend toward multi-functionality and high performance of mobile products. In the stack type multi-chip package, it is necessary to be able to select at least any one chip and apply an electrical signal to the selected chip.
FIG. 1 is a perspective view of a prior art stack package. FIG. 2 is a cross-sectional view of section A (the chip selection pad part) of FIG. 1, and FIG. 3 is a plan view of FIG. 1, showing an example of connecting chip selection pads using redistribution layers.
FIG. 1 shows a case in which semiconductor chips 20, 30, 40 and 50 are stacked on a substrate 10 and are connected with one another by means of through-silicon vias (TSVs) 24, 34, 44 and 54. A Vcc pad 12 and a Vss pad 14 are disposed on the substrate 10, and various I/O pads are disposed on the respective chips 20, 30, 40 and 50. Some of the I/O pads serve as chip selection pads 22, 32, 42 and 52 used for selecting chips. In the case where the same chips 20, 30, 40 and 50 are stacked using the through-silicon vias 24, 34, 44 and 54, since the chip selection pads 22, 32, 42 and 52 are placed at the same vertical position—that is, the pads 22, 32, 42 and 52 are stacked above each other—chip selection cannot be implemented using the through-silicon vias 24, 34, 44 and 54. Accordingly, redistribution layers 26, 36, 46 and 56 are formed on the respective chip selection pads 22, 32, 42 and 52 to be connected with through-silicon vias 28, 38, 48 and 58 which are placed at different positions. However, this method has a problem in that, since the redistribution layers 26, 36, 46 and 56 of the stacked chips 20, 30, 40 and 50 have different patterns, processing costs increase and difficulties exist in administrating processes.
FIG. 4 is a perspective view showing a prior art semiconductor package using wires for selecting a chip. Referring to FIG. 4, in the case where the same semiconductor chips 20, 30, 40 and 50 are stacked, since chip pads are positioned at the same positions on their respective chip, semiconductor chips 20, 30, 40 and 50 are stacked in a step-like shape to provide access to each pad, and chip selection pads 22, 32, 42 and 52 are connected with a Vcc pad 12 and a Vss pad 14 using wires W so as to be capable of applying chip selection signals to the semiconductor chips 20, 30, 40 and 50. Even in this stack configuration problems are caused in that wire bonding for chip selection increases the thickness of a package and the lengths of the wires W increase depending upon. The increased wire length causes signal delay and, the step-like stack configuration degrades the structural reliability of a package.